My doctoral research was focused on the hardware-software co-design of concurrent data structures with near-memory processing (NMP) architectures. This was a challenging problem, for the NMP-aware data structures had be carefully designed to preserve the high concurrency, correctness guarantees, and at times high on-chip cache locality provided by existing data structures which are highly optimized for conventional architectures. At the same time, they must take full advantage of the features and work around the challenges introduced by the new architecture.
I am now a software engineer at Apple. I am part of a team that builds SoC simulations for Apple hardware– if you are interested in joining our team, please send me an email with your resume.
In the SPAA ‘19 paper, NMP-based concurrent data structures that leverage the flat-combining synchronization scheme were implemented and evaluated on Brown-SMCSim, a cycle-accurate, full-system NMP architecture simulator. This yielded a more realistic and detailed performance, energy, and power analysis, compared to prior theoretical analysis. We showed that lightweight hardware modifications can significantly improve the performance and energy consumption of NMP-based concurrent data structures, even without any algorithmic changes. In many cases, the resulting data structures outperform state-of-the-art concurrent data structures.
The SPAA ‘22 paper addresses the limitation of NMP-based data structures found in the SPAA ‘19 paper. Hierarchical data structures that benefit from on-chip cache locality could result in reduced performance when all pointer-chasing activity is offloaded to near-memory compute units of the NMP architecture. In the SPAA ‘22 work, we present NMP-hybrid algorithms of such hierarchical data structures, which take advantage of both the on-chip cache locality of hierarchical data structures and the benefits of NMP architecture.
The fact that memory access operations require much more time and energy than simple logic operations in a traditional DRAM-based main memory architecture is exploited to build time-consuming and power-hungry memory-hard cryptographic functions, which serve the purpose of hindering brute-force security attacks.
The security of these memory-hard functions depend entirely on the non-trivial costs of memory access. However, various compute-capable memory technologies have recently emerged as promising ways around the memory wall. As a preliminary investigation into how compute-capable memory can impact the security of memory-hard functions, we looked into scrypt, a widely-used memory-hard PBKDF, and how it can be accelerated with near-memory processing.
I received my Bachelor’s degree in Electrical Engineering from Rice University (along with a dual degree in Computer Science). After Rice, I was at Oracle as a Software Engineer for 2.5 years, where I developed server hardware management tools.
I am a recipient the Cadence Women in Technology Scholarship. As part of the application, I wrote an essay about the challenges that I have faced as a female in STEM, and I recently found out that the essay had been shared on the Cadence blog! My story is not all that dramatic, but it is an honest reflection of how the discrimination towards women in STEM had misguided me in the past and how my own misperceptions may have harmed the community, even as a fellow woman.
Other random fun facts about me:
I love writing – yes, no joke! Not that it’s not painful, but I love the feeling when my ideas and thoughts get written down and become a coherent story.
I am also an avid coffee drinker. Some of my favorite coffee places are Bolt Coffee (Providence, RI), Borealis Coffee Company (Riverside, RI), Ritual Coffee Roasters (San Francisco, CA), Four Barrel Coffee (San Francisco, CA), and Devout Coffee (Fremont, CA).