My research interests are at the intersection of computer architecture and concurrent computing. I am particularly interested in the hardware-software co-design of concurrent data structures and algorithms with emerging memory technologies, such as compute-capable memory or non-volatile memory.
I am interested in improving the performance and energy efficiency of general-purpose concurrent data structures with Near-Data-Processing (NDP).
In the SPAA ‘19 paper, NDP-based concurrent data structures that leverage the flat-combining synchronization scheme were implemented and evaluated on Brown-SMCSim, a cycle-accurate, full-system NDP architecture simulator. This yielded a more realistic and detailed performance, energy, and power analysis, compared to prior theoretical analysis. We showed that lightweight hardware modifications can significantly improve the performance and energy consumption of NDP-based concurrent data structures, even without any algorithmic changes. In many cases, the resulting data structures outperform state-of-the-art concurrent data structures.
More recently, I have been looking into how “large yet cache-friendly” concurrent data structures can be integrated with NDP, in order to take advantage of concurrency, host processor cache locality, and computation near memory. The poster on Hybrid Skiplists summarizes the preliminary work in this direction.
The fact that memory access operations require much more time and energy than simple logic operations in a traditional DRAM-based main memory architecture is exploited to build time-consuming and power-hungry memory-hard cryptographic functions, which serve the purpose of hindering brute-force security attacks.
The security of these memory-hard functions depend entirely on the non-trivial costs of memory access. However, various compute-capable memory technologies have recently emerged as promising ways around the memory wall. As a preliminary investigation into how compute-capable memory can impact the security of memory-hard functions, we looked into scrypt, a widely-used memory-hard PBKDF, and how it can be accelerated with near-data-processing.
I received my Bachelor’s degree in Electrical Engineering from Rice University (along with a dual degree in Computer Science). After Rice, I was at Oracle as a Software Engineer for 2.5 years, where I developed server hardware management tools.
I am a recipient the Cadence Women in Technology Scholarship. As part of the application, I wrote an essay about the challenges that I have faced as a female in STEM, and I recently found out that the essay had been shared on the Cadence blog! My story is not all that dramatic, but it is an honest reflection of how the discrimination towards women in STEM had misguided me in the past and how my own misperceptions may have harmed the community, even as a fellow woman.
Other random fun facts about me:
I love writing – yes, no joke! Not that it’s not painful, but I love the feeling when my ideas and thoughts get written down and become a coherent story.
I am also an avid coffee drinker. Some of my favorite coffee places are Bolt Coffee (Providence, RI), Borealis Coffee Company (Riverside, RI), Ritual Coffee Roasters (San Francisco, CA), Four Barrel Coffee (San Francisco, CA), and Devout Coffee (Fremont, CA).